Quantum network coding for multi-unicast problem based on 2D and 3D cluster states
We mainly consider quantum multi-unicast problem over directed acyclic network, where each source wishes to transmit an independent message to its target via bottleneck channel. Taking the advantage of global entanglement state 2D and 3D cluster states, these problems can be solved efficiently. At first, a universal scheme for the generation of resource states among distant communication nodes is provided. The corresponding between cluster and bigraph leads to a constant temporal resource cost. Furthermore, a new approach based on stabilizer formalism to analyze the solvability of several underlying quantum multi-unicast networks is presented. It is found that the solvability closely depends on the choice of stabilizer generators for a given cluster state. And then, with the designed measurement basis and parallel measurement on intermediate nodes, we propose optimal protocols for these multi-unicast sessions. Also, the analysis reveals that the resource consumption involving spatial resources, operational resources and temporal resources mostly reach the lower bounds.
Opaque virtual network mapping algorithms based on available spectrum adjacency for elastic optical networks
Optical network virtualization enables multiple virtual optical networks constructed for different infrastructure users (renters) or applications to coexist over a physical infrastructure. Virtual optical network (VON) mapping algorithm is used to allocate necessary resources in the physical infrastructure to the VON requests (VRs). In this paper, we investigate the opaque VON mapping problems in elastic optical networks (EONs). Based on the concept of available spectrum adjacency (AvSA) on links or paths, we consider both node resource and AvSA on links for node mapping, and present a link mapping method which chooses the routing and spectrum plan whose AvSA on paths is the largest among all the candidates. Finally, the overall VON mapping algorithm (i.e., AvSA-opaque VON mapping, AvSA-OVONM) coordinated node and link mapping is proposed. Extensive simulations are conducted and the results show that AvSA-OVONM has better performance of blocking probability and revenue-to-cost ratio than current algorithms.
Self-mixed self-interference analog cancellation in full-duplex communications
Rather than using existing self-interference cancellation methods, which essentially consist of reconstruction and subtraction, this paper proposes a novel approach, based on multiplication, to cancel selfinterference in the analog domain in full-duplex communications. This approach is called self-mixed selfinterference analog cancellation (SM-SIAC). Moreover, rather than using an individual analog cancellation circuit in existing self-interference cancellation methods, SM-SIAC can merge the analog cancellation circuit and the receiver. SM-SIAC is configured with three auto-tuning loops, consisting of one delay loop and two gain loops. SM-SIAC is further simplified with the Gaussian minimum shift keying (GMSK) self-interference signal. When these loops converge, the paper analyzes the cancellation capacity and derives a closed-form expression for the quadrature amplitude modulation self-interference signal and the GMSK self-interference signal. Simulation results illustrate the convergence of the gain loops and the cancellation capacity in the presence of engineering errors.
Value locality based storage compression memory architecture for ECG sensor node
This paper proposes a value compression memory architecture for QRS detection in ultra-low-power ECG sensor nodes. Based on the exploration of value spatial locality in the most critical preprocessing stage of the ECG algorithm, a cost efficient compression strategy, which reorganizes several adjacent sample values into a base value with several displacements, is proposed. The displacements will be half or quarter scale quantifications; as a result, the storage size is reduced. The memory architecture saves memory space by storing compressed data with value spatial locality into a compressed memory section and by using a small, uncompressed memory section as backup to store the uncompressed data when a value spatial locality miss occurs. Furthermore, a low-power accession strategy is proposed to achieve low-power accession. An embodiment of the proposed memory architecture has been evaluated using the MIT/BIH database, the proposed memory architecture and a low-power accession strategy to achieve memory space savings of 32.5% and to achieve a 68.1% power reduction with a negligible performance reduction of 0.2%.
Single event upset rate modeling for ultra-deep submicron complementary metal-oxide-semiconductor devices
Based on the integral method of single event upset (SEU) rate and an improved charge collection model for ultra-deep submicron complementary metal-oxide-semiconductor (CMOS) devices, three methods of SEU rate calculation are verified and compared. The results show that the integral method and the figure of merit (FOM) methods are basically consistent at the ultra-deep submicron level. By proving the validity of the carrier collection model considering charge sharing, the applicability of two FOM methods is verified, and the trends of single-bit and multiple-bit upset rates for ultra-deep submicron CMOS are analyzed.
Dynamically reconfigurable architecture for symmetric ciphers
In this paper, a very large scale integration (VLSI) architecture for a reconfigurable cryptographic processor is presented. Several optimization methods have been introduced into the design process. The inter-connection tree between rows (ICTR) method reduces the interconnection complexity and results in a small area overhead. The hierarchical context organization (HCO) scheme reduces the total context size and increases the dynamic configuration speed. Most symmetric ciphers, including AES, DES, SHACAL-1, SMS4, and ZUC, can be implemented using the proposed architecture. Experimental results show that the proposed architecture has obvious advantages over current state-of-the-art architectures reported in the literature in terms of performance, area efficiency (throughput/area) and energy efficiency (throughput/power).
Ultralow-power high-speed flip-flop based on multimode FinFETs
In this paper, we first reconstruct a novel planar static contention-free single-phase-clocked flipflop (S2CFF) based on high-performance fin-type field-effect transistors (FinFETs) to achieve high speed and ultralow power consumption. Benefiting from better control of the conductive channel, the shorted-gate (SGmode) FinFET flip-flop obtains a persistent reduction of 56.7% in average power consumption as well as a considerable improvement in timing performance at a typical 10% data switching activity, while the low-power (LP-mode) FinFET flip-flop promotes the power reduction to 61.8% without appreciable degradation in speed. However, through further analysis of the simulation results, we have revealed an unnecessary energy loss caused by the redundant leaps of internal nodes at the static input ‘0’, which has a noticeable negative impact on total power consumption at low data switching activity. In order to overcome this defect, a conditional precharge technique is introduced to control the charging path, and we demonstrate that the independent-gate (IG-mode) FinFET is the best option for the added control transistor. The verification results indicate that our optimization reduces the power consumption by more than 50% at low data switching activity with an acceptable area and setup time penalty compared with that of LP-mode FinFET flip-flop.
Novel wavelet neural network algorithm for continuous and noninvasive dynamic estimation of blood pressure from photoplethysmography
This paper proposes a novel wavelet neural network algorithm for the continuous and noninvasive dynamic estimation of blood pressure (BP). Unlike prior algorithms, the proposed algorithm capitalizes on the correlation between photoplethysmography (PPG) and BP. Complete BP waveforms are reconstructed based on PPG signals to extract systolic blood pressure (SBP) and diastolic blood pressure (DBP). To improve the robustness, Daubechies wavelet is implemented as the hidden layer node function for the neural network. An optimized neural network structure is proposed to reduce the computational complexity. Further, this paper investigates an inhomogeneous resilient backpropagation (IRBP) algorithm to calculate the weight of hidden layer nodes. The IRBP improves the convergence speed and reconstruction accuracy. Multiparameter intelligent monitoring in Intensive Care (MIMIC) databases, which contain a variety of physiological parameters captured from patient monitors, are used to validate this algorithm. The standard deviation σ between reconstructed and actual BP signals is 4.4797 mmHg, which satisfies the American National Standards of the Association for the Advancement of Medical Instrumentation. The reconstructed BP waveform can be used to extract the SBP and DBP, whose standard deviations σ are 2.91 mmHg and 2.41 mmHg respectively.
Improved quantum ripple-carry addition circuit
A serious obstacle to large-scale quantum algorithms is the large number of elementary gates, such as the controlled-NOT gate or Toffoli gate. Herein, we present an improved linear-depth ripple-carry quantum addition circuit, which is an elementary circuit used for quantum computations. Compared with previous addition circuits costing at least two Toffoli gates for each bit of output, the proposed adder uses only a single Toffoli gate. Moreover, our circuit may be used to construct reversible circuits for modular multiplication, Cx mod M with x<M, arising as components of Shor's algorithm. Our modular-multiplication circuits are simpler than previous constructions, and may be used as primitive circuits for quantum computations.
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process
A novel, area-efficient transient power-rail electrostatic discharge (ESD) clamp circuit is proposed in this work. Current-mirror capacitors are used to reduce the layout area. Logic threshold voltages of inverters are modified to ensure a fully active on-state for the clamp device in ESD conditions. The proposed circuit reduces the layout area by about 56% compared with a circuit without current-mirror capacitors. Transmission line pulse (TLP) test results based on a 65-nm CMOS process demonstrate that the proposed circuit is an efficient on-chip ESD protection scheme for this process. In addition, the proposed circuit achieves a good immunity to mis-triggering with respect to fast power-up transitions.
LSB page refresh based retention error recovery scheme for MLC NAND Flash
NAND Flash memories present inevitable decline in reliability due to scaling down and multilevel cell (MLC) technology. High retention error rate in highly program/erase (P/E) cycled blocks induces stronger ECC requirement in system, causing higher spare bits cost and hardware overhead. In this paper, a least significant bit (LSB) page refresh based retention recovery scheme is proposed to improve the retention reliability of highly scaled MLC NAND Flash. As in the scheme, LSB page refresh operation induces floating gate electron re-injection to compensate charge leakage during long retention time, and realizes retention error rate reduction. Experiment result on 2x-nm MLC NAND Flash exhibits more than 78% retention error rate reduction. Compared with reported retention error recovery scheme, the proposed scheme presents 2.5 times recovery efficiency promotion and 60% latency reduction.
A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure
This paper proposes a 256×256 time-of-flight (TOF) image sensor based on the center-tap (CT) demodulation pixel structure. The image sensor can capture both the two-dimensional (2D) high speed image and the three-dimensional (3D) depth image. The CT pixel consists of two split pinned photodiode (PPD) regions and two pairs of transfer transistors. The transfer transistors adopt a non-uniform doped channel (NUDC) structure, which can increase the electron transfer speed along the transfer channel and eliminate the image lag for high speed imaging. The pixel size is 10 μm×10 μm, and we design the implementation process of the pixel to increase the electron transfer speed. The sensor is fabricated in a 0.18 μm 1P5M CMOS image sensor process. Test results show that it can capture the 430-fps intensity image and the 90-fps depth image in two different imaging modes. The rectified non-linearity within the 1.0-7.5 m depth measurement range achieves less than 3 cm, and the measurement accuracy achieves 4.0 cm at 2.5 m, corresponding to the relative error of 1.6%.
Novel high voltage RESURF AlGaN/GaN HEMT with charged buffer layer
A novel reduced surface field (RESURF) AlGaN/GaN high electron mobility transistor (HEMT) with charged buffer layer is proposed. Its breakdown mechanism and on-state characteristics are investigated. The HEMT features buried Fluorine ions in the GaN buffer layer both under the Drift and the Gate region (FDG). The section of FDG under the drift region (FD) not only reduces the electric field (E-field) peak at the gate edge but also enhances the E-field in the drift region by the assisted depletion, leading to a significant improvement in breakdown voltage (BV). Moreover, the section of FDG under the gate (FG) enhances the back barrier and effectively prevents electron injecting from the source to form leakage current, thus a higher BV is achieved. The BV of the proposed HEMT sharply increases to 750 V from 230 V of conventional Al-GaN/GaN HEMT with the same dimensional parameters, and the specific on-resistance (Ron,sp) just increases to 1.21 mΩ·cm2 from 1.01 mΩ·cm2.
Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology
Single event upset (SEU) is one of the most important origins of soft errors in aerospace applications. As technology scales down persistently, charge sharing is playing a more and more significant effect on SEU of flip-flop. Charge sharing can often bring about multi-node charge collection in storage nodes and non-storage nodes in a flip-flop. In this paper, multi-node charge collection in flip-flop data input and flip-flop clock signal is investigated by 3D TCAD mixed-mode simulations, and the simulate results indicate that single event double transient (SEDT) in flip-flop data input and flip-flop clock signal can also cause a SEU in flip-flop. This novel mechanism is called the SEDT-induced SEU, and it is also verified by heavy-ion experiment in 65 nm twin-well process. The simulation results also indicate that this mechanism is closely related with the well-structure, and the triple-well structure is more effective to increase the SEU threshold of this mechanism than twin-well structure.
A low-complexity sensor fusion algorithm based on a fiber-optic gyroscope aided camera pose estimation system
Visual tracking, as a popular computer vision technique, has a wide range of applications, such as camera pose estimation. Conventional methods for it are mostly based on vision only, which are complex for image processing due to the use of only one sensor. This paper proposes a novel sensor fusion algorithm fusing the data from the camera and the fiber-optic gyroscope. In this system, the camera acquires images and detects the object directly at the beginning of each tracking stage; while the relative motion between the camera and the object measured by the fiber-optic gyroscope can track the object coordinate so that it can improve the effectiveness of visual tracking. Therefore, the sensor fusion algorithm presented based on the tracking system can overcome the drawbacks of the two sensors and take advantage of the sensor fusion to track the object accurately. In addition, the computational complexity of our proposed algorithm is obviously lower compared with the existing approaches (86% reducing for a 0.5 min visual tracking). Experiment results show that this visual tracking system reduces the tracking error by 6.15% comparing with the conventional vision-only tracking scheme (edge detection), and our proposed sensor fusion algorithm can achieve a long-term tracking with the help of bias drift suppression calibration.
Investigation of plasmonic whispering gallery modes of graphene equilateral triangle nanocavities
In this paper, a graphene-based equilateral triangle nanocavity is proposed and numerically investigated. The relationship between the mode characteristics and the nanocavity parameters, such as the geometry of nanocavity and the chemical potential of graphene, is systematically explored. A high-order plasmonic WGM (whispering gallery mode) with a high quality factor of 147.93 is obtained in our nanocavity with a wavelength of around 1.415 μm in free space, with a corresponding Purcell factor as high as 7.067×108. The proposed plasmonic WGM nanocavity could be a key component of the high density plasmonic integrated circuits due to its ultra-compactness and performances.
Tailoring electromagnetically induced transparency effect of terahertz metamaterials on ultrathin substrate
Electromagnetically induced transparency (EIT) is a fascinating phenomenon in optical physics and has been employed in slow light technology. In this work, we use terahertz (THz) metamaterials to mimic EIT phenomenon and study their spectral dependence on the coupling strength between bright and dark resonators. In these metamaterials, two kinds of resonators are located on two different layers separated by a 10-μm-thick polyimide (PI) film. The whole sample is supported by a 5-μm-thick flexible PI film, so the Fabry-Perot resonance at THz can be avoided. The coupling strength is tuned by the translational offset of symmetry axes between two different kinds of resonators, resulting in the change of EIT-like spectra.
Adaptively secure ciphertext-policy attribute-based encryption with dynamic policy updating
Attribute-Based Encryption (ABE) is a promising new cryptographic technique which guarantees fine-grained access control of outsourced encrypted data in the cloud. With the help of ABE, the majority of security issues in accessing cloud data can be solved. However, a key limitation remains, namely policy updating. Whenever the access policy is updated, a common approach is to have the data owner retrieve the data and re-encrypt it with new policy, before sending the new ciphertext back to the cloud. This straight-forward approach will lead to heavy computation and communication overhead. Although a number of other approaches have been proposed in this regard, they suffer from two limitations; namely, supporting only limited update-policy types or having weak security models. In order to address these limitations, we propose a novel solution to the attribute-based encryption access control system by introducing a dynamic policy-updating technique which we call DPU-CP-ABE. The scheme is proved to be adaptively secure under the standard model and can support any type of policy updating. In addition, our scheme can significantly reduce the computation and communication costs of updating ciphertext.
Smart world:a better world
With the advancement of technologies, our world is becoming a smart world. In this paper, we share our vision of a smart world, demonstrate different application scenarios and introduce the emerging techniques. We envision that in a smart world, we will become more connected, safe, productive and efficient. To enable a smart world, many advanced techniques such as advanced network, ubiquitous sensing and collaborative computation have been developed. More specifically, they include heterogeneous advanced wireless networks, intelligent transportation, accurate indoor localisation, wireless sensor network, unobtrusive human behaviour sensing and mobile cloud computing. Compared with the previous work, the proposed techniques are faster, more accurate and non-invasive. We firmly believe that by exploiting those techniques, the smart world will be a better world.
Biclique cryptanalysis using balanced complete bipartite subgraphs